5th Workshop Technical Program
(Dec. 4-6, 2000)

Welcome and Invited Talks  (Monday, Dec. 4, 2000, 10:00-12:00)
  Chair:  K. Otsuka, Meisei Univ.

1.  Opening Remarks
    F. Ishitsuka, NTT Electronics

2.  Packaging Design Considerations for High-Speed Memory Bus
    H. J. Liaw, N. Naono and D. Secker, Rambus Inc.

3.  Multi-Gb/s CMOS LSI Design and Requirements for LSI Packages
    Y. Ohtomo, M. Nogawa and Y. Kitamura, NTT

4.  High-Performance 80nm Gate Length SOI-CMOS Logic Technology with Full Level Dual Damascene Cu /Very Low -k Interconnects
    M. Yamada, Fujitsu Ltd.

Session 1:  3-D Packages  (Monday, Dec. 4, 2000, 13:00-15:30)
  Co-Chairs:  H. W. Lee and M. Kohno

1.1  Z-axis Interconnections for High Density Processors
     Len Schaper, Univ. of Arkansas

1.2  Three Dimensional Stacked Module Structure
     T. Sato, N. Tanaka and K. Takahashi, ASET

1.3  Novel High-Volume Manufacturing Technology for 3D IC Packages
     J. Reche, P. Halahan and R. Korczynsky, Tru - Si Technologies

1.4  The Same Die Stack CSP Packages: Enabling Flexibility in Chip Stacking
     Flynn Carlson, ChipPAC, Inc.

1.5  Tessera Stacked Die CSP Technology
     M. Warner, Tessera

Session 2:  Electrical Performance  (Monday, Dec. 4, 2000, 16:00-18:00)
  Co-Chairs:  T. Sudo and L. Schaper

2.1  Measurement Evidence of Mirror Potential Traveling on Transmission Lines
     K. Otsuka, T. Usami, Y. Ohdate* and Y. Ikemoto** ,Meisei Univ., *Univ. of Tokyo, **Fujitsu Ltd.

2.2  Measurement Study for Lower Impedance Transmission Lines by the 50 Ohm Set-up and Consequent Performance Comparison between SPL and MSL with High Accuracy
     Y. Ikemoto, T. Usami* and K. Otsuka* , Fujitsu Ltd., *Meisei Univ.

2.3  Power Supply for High-speed Signal
     Y. Odate, T. Usami*, K. Otsuka* and T. Suga, Univ. of Tokyo, *Meisei Univ.

2.4  Signal Transmission in Multi-chip Module Ball Grid Array
     C. P. Hung, C. C. Tu, J. S. Hsieh and J. J. Lee, ASE, Taiwan

Session 3:  Process/Materials  (Tuesday, Dec. 5, 2000, 8:50-10:20)
  Co-Chairs:  Y. Hirata and N. Iwasaki

3.1  Studies on Wettability between Solder Bump and Substrate Finishes for Reflowable Underfill Application
     T. Wang, C. Lum, P. Miao, T. H. Chew and L. Foo, Questech Solutions Pte Ltd.

3.2  BCB Polymer Dielectrics for Electronic Packaging and Build-up Board Applications
     K. Ohba, M. Kohno, J. H. Im*, P. Garrou* and T. Komiyatani**, Dow Chemical Japan, *Dow Chemical USA, **Sumitomo Bakelite Co., Ltd.

3.3  Combination Technology of Low Warpage Epoxy Resin and Vacuum Printing Encapsulation Systems (VPES) for Stacked IC
     A. Okuno, N. Ohyama and Y. Ogisu, Japan Rec Co., Ltd.

Session 4:  CSP/New Package Structure  (Tuesday, Dec. 5, 2000, 10:30-12:30)
  Co-Chairs:  H. Kasuga and E. J. Vardaman

4.1  Copper Bump Bonding Technologies on 3D Stacked Devices
     Y. Tomita, M. Tago, Y. Nemoto and K. Takahashi, ASET

4.2  New CSP Using the Reversible Interconnection Concept
     M. Onodera and T. Suga, Univ. of Tokyo

4.3  Development of TBGA-´┐ŻUPackage: High Power Package with Active Ground Plane
     Young Heo, ChipPAC, Inc.

4.4  Reliability of the S3-Diepack WLP
     J. Simon, TU of Berlin & Fraunhofer IZM

Session 5:  Fine-pitch Interconnection (1)  (Tuesday, Dec. 5, 2000, 13:30-15:00)
  Co-Chairs:  Y. Kohara and G. Harman

5.1  Trends in Flip Chip Packaging: The Ultimate Wafer Level Package
     E. J. Vardaman, TechSearch International

5.2  Room Temperature Interconnection of Electroplated Au Microbump by means of Surface Activated Bonding Method
     Y. Matsuzawa, T. Itoh and T. Suga, Univ. of Tokyo

5.3  Evaluation of Solder Joint reliability of DCA Assembly by Temperature Cyclic Test, Bending Test, Shear Test and Drop Test
     P. J. Zheng, S. H. Ho, C. W. Lee, H. J. Kung, J. Z. Lee, J. D. Wu and J. G. Hwang, ASE, Taiwan

Session 6:  Thermal/Mechanical Characterization  (Tuesday, Dec. 5, 2000, 15:30-17:00)
  Co-Chairs:  T. Ohde and Sheng Liu

6.1  Characterization of Mechanical Failure Mechanisms in Small Area Array IC Package
     T. Gregorich, T. Marburger and M. Velez, Qualcomm

6.2  Thermal Characterization of Stacked-Die BGA
     L. W. Lee, J. G. Hwang, H. N. Chen and J. T. Wu, ASE, Taiwan

6.3  The Relationship between Substrate Components and Thermal Performance / Stress Issues of Chip Scale Packages
     T. C. Huang, L. W. Lee, C. C. Lee, D. P. Lai and J. G. Hwang, ASE, Taiwan

6.4  Board Level Thermal Simulation System for LSI Packages
     N. Yoneda, M. Kitano, H. Miura, I. Shimizu and N. Koike, Hitachi

Panel Discussion:  Technologies for High-Performance Systems  (Tuesday, Dec. 5, 2000, 17:30-19:00)
  Chair:  A. Nakamura
  Panelists:  L. Schaper, H. J. Liaw, K. Otsuka, M. Yamada and T. Sudo

Session 7:  Modules and Optical Applications  (Wednesday, Dec. 6, 2000, 8:50-10:20)
  Co-Chairs:  H. Shibata and J. L. Prince

7.1  High-density 3D Packaging Technology for CCD Micro-camera System Module
     H. Yamada, T. Togasaki, M. Kimura and H. Sudo, Toshiba Corp.

7.2  System in Package using Chip Stacking Technology
     Y. Uchida, Y. Saeki and T. Oka, Oki

7.3  Electrical Interconnection Techniques for 40-Gb/s Optical Receiver Module
     N. Iwasaki, M. Yanagibashi, H. Tsunetsugu, F. Ishitsuka and M. Hosoya, NTT

Session 8:  Fine-pitch Interconnection (2)  (Wednesday, Dec. 6, 2000, 10:30-12:00)
  Co-Chairs:  N. Kamehara and T. Mimura

8.1  Material, Problems, Solutions for Wire Bonding to Advanced Copper Low-K Integrated Circuits
     G. G. Harman, NIST.

8.2  Ultrasonic Flip-chip Bonding Technology using Preformed Underfill Resin
     T. Iwasaki, S. Yamada, M. Kimura, Y. Hatanaka, H. Fujioka and N. Ueda, Mitsubishi

8.3  Room Temperature Direct Bonding of CMP-Cu Film
     A. Shigetou, N. Hosoda, T. Itoh and T. Suga, Univ. of Tokyo

Closing Remarks  (Wednesday, Dec. 6, 2000, 12:00)