Plenary and invited Speakers

Last update: April 19, 2018

Plenary Speakers

Toru Baji (NVIDIA)

Clint Schow (University of California, Santa Barbara)

Daniel Kuchta (IBM T. J. Watson Research Center)
"New Packaging Alternatives via high bandwidth and low power USR SerDes"
Amin Shokrollahi (Kandou BUS)

Massive integration of IC components on a chip has been the primary catalyst for the development of high performance Systems on Chip (SoC). Today, SoC’s contain a multitude of components besides the logic core that makes up the main functionality. Integration of these components is fast becoming the major bottleneck in the design and development of SoC’s. Verification alone can take up to 70% of the design time, especially when high speed analog components have to be integrated alongside digital ones. The tide is therefore changing in the industry, with disintegration gaining more traction.
“Chiplets”, or stand alone die with defined functions in heterogenous processes, can be packaged together to create a disintegrated SoC. To allow maximum flexibility in terms of die placement and heterogeneity, as well as lowest packaging costs, ultra-short-reach (USR) SerDes can be used to connect chiplets in a standard MCM. For such SerDes to be competitive, it needs to have extremely high bandwidth, and be of lowest possible power.
In this talk I will introduce such a SerDes family, called “Glasswing,” discuss some of the theory behind its development, and outline today’s and future applications.


EPS Special Speakers

Chris Bailey (University of Greenwich)



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