Last update: November 8, 2023

Plenary Speakers
"New Level Innovation of Advanced Heterogeneous Integration"
Seung Wook Yoon (Samsung Electronics Co., Ltd.)

Abstract: Pandemic shifts in surrounding circumstances have been driving a massive data transformation in the semiconductor industries recently. The largest growth applications come from the autonomous vehicle and HPC/AI as part of the smart world expansion and data explosion.
As thirst for more data bandwidths and added functions intensifies, the advanced packaging has garnered much interest as one of the key potential solution. The value of advanced packaging technology is to enable the heterogeneous integration. Advances in heterogeneous chip packages are needed to empower today's device manufacturers to pursue tomorrow's breakthroughs. Both 2.xD and 3D variations will be needed to keep innovation vibrant.
For high-performance computing (HPC), a 2.xD package has been developed based on a silicon interposer, embedded silicon bridge or re-distribution layer (RDL) interposer to integrate multiple logic devices including chiplets and memory, allowing higher data transfer system capability. The next-generation 3D packages are based on the chiplet technology, where logic or memory dies are placed on top of the logic die or vice versa. Further down the line, the combination of 3D and 2.xD interposer technologies, also known as the 3.5D technology, will contribute in our quest to fulfil the needs of ultra-high-performance in data transfer and minimization of system package form factor.
In this paper, Samsung advanced package platform including X-Cube, full 3D solution, is to be introduced in terms of roadmap, technical challenges and opportunities for emerging high-end computing, memory and mobile applications. Also will discussed current activities of advanced PKG and UCIe chiplet standardization and industrial collaboration in ecosystem across all chip companies, design partners and foundries in the ecosystem (EDA, IP, DPS memory, OSAT, substrate and testing) for system integration and products innovation.

"Optical I/O Chiplets and Architectures for Computing Fabrics"
Mark Wade (Ayar Labs)

Abstract: Ever increasing SoC package-to-package bandwidths are creating challenging requirements for die edge bandwidth density, power consumption, and reach. Recent advances in generative AI have accelerated the need for next-generation computing interconnects. To meet the requirements, optical chiplets that leverage advanced packaging have emerged as a viable solution This presentation summarizes trends in applications, optical chiplets and requirements for computing fabrics, and forward looking roadmap projections.

"Co-Package Optics is the big next thing: What happened?"
Daniel M. Kuchta (IBM Thomas J. Watson Research Center)

Abstract: Co-packaged optics was supposed to be the next latest & greatest technology that promised to be the IO solution starting with the 51T ethernet switch generation and continuing onwards. But with limited exceptions, this is not occurring. So, what happened? This talk will explore the current status of co-packaging efforts, both VCSEL and SiPh, and where they fit in to the Ethernet switch and the evolving Computer IO markets.

"Latest Advanced Packaging Solutions for Heterogeneous Integration"
C.P. Hung (ASE Group)

Abstract: Advanced packages deliver the highest density interconnect between chips and are implemented as pivotal enabling technologies for ultrahigh performance module or system. This presentation will explore the design variation, structural difference and developing challenges of the advanced packages for new generation heterogeneous integration to applications on AI server, data center and automotive computing.


IEEE EPS Special Speakers
"Supply Chain Trends, Challenges, and Disruptions in Semiconductor Packaging"
Kitty Pearsall (Boss Precision, Inc.)

Abstract: The semiconductor packaging market is continuing to grow as the global industry recovers from Covid. The impact of the pandemic itself was readily apparent in its supply chain. As a result, the importance of the supply chain (SC) was brought to the forefront of the global semiconductor manufacturers. The significance of this is great since the semiconductor market is estimated to be $532 Billion this year and the global supply chain management market is stated as approximately 29 billion dollars with a CAGR of 10.7% (ResearchAndMarkets.com).
Emerging market applications continue to drive this growth through applications that include automotive, medical, health, wearables, mobile and telecommunications, high-performance computing, smart manufacturing, internet of things, and artificial intelligence.
It is noted that the assembly package manufacturing process that some OSATs, OEMs, and foundries had become: over-reliant on single-source suppliers; focused heavily on cost optimization; had limited/minimal SC transparency; and depended on "just-in-time" production methodology to minimize inventory. There are more challenges facing manufacturers than these. All of these make the manufacturer more vulnerable and less agile and less flexible to any type of disruption. KPMG highlighted that "95% of supply chains must quickly react to changing conditions, but only 7% are able to execute decisions in real time".
This brief presentation will provide SC trends, challenges, and potential future SC directions important to the semiconductor supply chain of OSATs, OEMs, and foundries.

"Design Challenges with Chiplets"
Sam Karikalan (Broadcom Inc.)


Special Speakers
"Challenges for hetero integration: process technology, test and reliability"
Harald Kuhn (Fraunhofer ENAS)

Abstract: The rapidly evolving landscape of semiconductor technology demands innovative approaches to overcome the challenges of hetero-integration in process technology, test and reliability. This presentation explores key aspects, highlighting three critical areas for a wide range of micro assembly applications: wafer bonding technology, digital twins and AI in process control, and test and reliability for power semiconductors. By examining these key areas, this presentation provides valuable insights into the intricacies and solutions with hetero-integration, driving innovation, research and future advancements for use with the next generation semiconductor test applications.

"Strategical Positioning of AIST Open R&D platform on Advanced Logic Semiconductors Technology"
Yoshihiro Hayashi (AIST / Keio University)

Abstract: Moore's law has been kept on transistor number per unit area, while the device structure has been being evolved from planar MOSFET via 2.5D FinFET to 3D GAAFET with high-k/metal replacement gate-stuck, possibly enhancing RF/analog performances. Under the NEDO's R&D project, "Post-5G information communication system infrastructure strengthening" (JPNP20017), basic researches has been kicked off, focusing on the device physics and process phyco-chemistry for these logic-semiconductor devices since 2021. The pilot-line is to be provided for the technology sharing with not only device and tool venders but also system users and universities under "Consortium for Advanced Semiconductor Manufacturing Technology (ASMA)".

"Dynamic Wireless Power Transfer Technologies for Future Electric Vehicles"
Takehiro Imura (Tokyo University of Science)


Invited Speakers
"2.5D Photonic Integration for GPU Interconnects"
Benjamin G. Lee (NVIDIA)
"Energy-Efficient Integrated Photonics for Future Optical Interconnects and Neuromorphic Computing"
Stanley Cheung (Hewlett Packard Labs)
"Photonic System-in-Package (pSiP) by applying thin glass"
Henning Shröder (Fraunhofer IZM)
Advanced Packaging:
"Metal-polymer direct joining using small textures on metal surface"
Yusuke Kajihara (The University of Tokyo)
"Changes in Surface Functional Groups and Adhesion Strength to Heterogenous Material of UV Irradiated Epoxy-based Resin"
Takeyasu Saito (Osaka Metropolitan University)
Process and Material Technologies:
"Laser-assisted high-throughput integration of microLEDs"
Sergio Roso (Holst Centre)
"Atomic imaging of Al2O3/diamond interface by photoelectron holography"
Mami N. Fujii (Kindai University)
Power Electronics:
"350℃ operation of SiC complementary JFET logic gates"
Mitsuaki Kaneko (Kyoto University)
"The Cutting-edge Simulation and Validation Technology using Model-based Development"
Markus Plöger (dSPACE GmbH)
SI / PI / RF / EMC:
"Challenges of Semiconductor Microfabrication Technology for 3D Chiplet Integration"
Yasuhiro Morikawa (ULVAC, Inc.)
IEEE EPS Technical Committee 6 ~ Challenges of Large Size Organic Substrate:
"Large Substrate Manufacturing and Assembly Challenges"
Richard Graf (Marvell)
"Development of Chip-last Ultra Large Organic Package"
Kyota Yamamura (Shinko)
"Risk of Delamination in Larger Substrate and Mitigation"
S.B. Park (The State University of New York)
"Organic Core & Prepreg Materials for Large Size Substrate"
Masahisa Ose (Resonac)
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