Technical Program of 1st Workshop
(Nov. 30-Dec. 2, 1992)

Welcome and Invited Paper Session  (Monday, Nov. 30, 1992, 10:00-12:30)
  Chair:  Kanji Otsuka, Hitachi

1.  Opening Remarks
    K. Otsuka, Hitachi

2.  Packaging Technology for the PC 9800 (Invited)
    K. Moritani, K. Fujinami and Y. Ikeda, NEC

3.  Packaging for Video Camera-Recorders (Invited)
    M. Fujisaku, Matsushita

4.  Technology Changes That Affect Packaging (Invited)
    J. W. Balde, IDC
Session 1:  High Density Packaging  (Monday, Nov. 30, 1992, 13:30-15:35)
  Co-Chairs:  Dennis R. Olsen, Motorola and Kenzo Hatada, Matsushita

1.1  Lead On Chip Package Development
     J. Arita, I. Anjoh, A. Nishimura and M. Ichitani, Hitachi Ltd., Japan

1.2  OMPAC, "A New Kid on the Block"
     J. Sloan, V. Nomi, H. Wilson, Motorola, USA

1.3  Low Profile, 3-D Memory for Portable and Hand Held Applications
     M. F. Suer, R. Some, T. Johnson and S. Shanken, Irvine Sensors Corp., USA

1.4  High Density Memory Packaging with Vertical Surface Mount Package (VPAK)
     T. Chiu, N. McLellan and W. Schroen, TI, USA

1.5  Simulation of Radioactive Impurities and Electrical Properties of LOC Packages
     T. Yoshida and K. Hatada, Matsushita Electric, Japan
Session 2:  Electrical Modeling and Simulation  (Monday, Nov. 30, 1992, 16:05-18:10)
  Co-Chairs:  Hans Hentzell, Linkoping Univ. and Toshio Sudo, Toshiba

2.1  Minimization of Effective Inductance of Ground Plane and Experimental Simultaneous Switching Noise in a Multilayer VLSI Package
     N. Hirano, Y. Hirata and T. Sudo, Toshiba Corp., Japan

2.2  Current Distribution Analysis for Power/Ground Planes of VLSI Packages
     K. Nakamata, M. Nishimura and S. Ninomiya, Kyocera Corp., Japan

2.3  Cost Effective Inductance Calculation Using Personal Computers
     A. Nakamura, T. Miwa and K. Otsuka, Hitachi Ltd., Japan

2.4  Impact of Reference Plane Parasitics on the System Noise in High Speed Applications
     J. L. Prince, R. Senthinathan, A. C. Cangellaris and K. Russell, Univ. of Arizona, USA

2.5  3-D EM Field Analysis Using the Spacial Network Method and Its Application to a High-Frequency Package
     R. Konno and N. Kukutsu, NTT, Japan
Session 3:  High Performance Package Design  (Tuesday, Dec. 1, 8:00-9:40)
  Co-Chairs:  Elaine Pope, Intel and Hisashi Tomimuro, NTT

3.1  Shielded Differential Coplanar Transmission Lines: A New Structure for Very High Speed Packages Design
     M. Bedouani, Bull, France

3.2  High Lead Count and High Performance Ceramic QFP
     Y. Nakatsuka, Y. Morita, M. Fujii and Y. Miura, Sumitomo Metal Industries, Japan
     H. Ohtani, E. Takahashi, Sumitomo Metal Ceramics Inc., Japan

3.3  Development of High Density Down-Sizing PGA by Super Fine Pitch Pattern for High Speed Application
     M. Miura, T. Kudo, H. Ohtani and F. Matsunaga, Sumitomo Metal Ceramics, Japan

3.4  Time and Frequency Domain Characterization of Pin Grid Array for High Speed Digital Gate Arrays
     T. W. Goodman, H. Fujita and Y. Murakami, Sony Corp., Papan
     A. T. Murphy, DuPont, USA
Session 4:  Reliability of VLSI Packaging  (Tuesday, Dec. 1, 10:10-11:50)
  Co-Chairs:  Wulf H. Knausenbeger, AT&T and Hiroshi Shibata, Mitsubishi

4.1  Reliability Studies on Thin Package
     K. Shimomura, T. Ueda, I. Sasaki, T. Tachikawa and K. Nakagawa, Mitsubishi Electric, Japan

4.2  Estimation of Vapour Pressure in the Plastic Package during Reflow Soldering
     K. Sawada, H. Mukaida, S. Itoh, T. Nakazawa, N. Kawamura and N. Izawa, Toshiba Corp., Japan

4.3  Obtaining High Quality VLSI Package with QPP
     K. Feameil and R. Raines, IBM, USA

4.4  Thermal Strain of the Bonding Stage at the Gang Bonding Process
     T. Hashimoto, M. Yasunaga and T. Kondoh, Mitsubishi Electric, Japan
Session 5:  Thermal and High Speed Signal Management  (Tuesday, Dec. 1, 19:00-20:40)
  Co-Chairs:  Les Fox, DEC and George G. Harman, NIST

5.1  Air Cooling of MCMs Mounted on Card-on-board Packaging System
     A. Harada, Y. Kaneko and T. Kishimoto, NTT, Japan

5.2  Immersion Cooling of Multi Chip Modnles with Fluorinert Liquids in an Enclosed System
     H. Kristiansen, T. Gleditsch and A. Bjoreklett, Center for Industrial Research
     Dolphin SCI Technology A/S, Norway

5.3  Packaging Techniques for the 620Mb/s High Speed Switching Module
     M. Yamada, T. Handa, S. Iida and J. Utsunomiya, Oki Electric, Japan

5.4  Electrical Modeling of 3D Structures in MCM Interconnect
     R. Beck, R. Brodowski and R. Dumcke, Technical University of Berlin, Germany
Session 6:  Package Manufacturing Technology  (Tuesday, Dec. 1, 21:00-22:40)
  Co-Chairs:  Justin C. Bolger, Emerson & Cuming and Teruo Kosaka, NEC

6.1  The Performance of a CVD Diamond Bonding Tool
     K. Tanaka, Sumitomo Electric Industries, Japan

6.2  High Reliability Wire Bonding Technology by the 120kHz Frequency of Ultrasonic
     T. Miwa and K. Otsuka, Hitachi Ltd., Japan
     T. Araki, I. Seki. K. Kikuchi and N. Fujita, Hitachi Hokkai Semiconductor, Japan

6.3  Development of Precoat Soldering Technology for Volume Production Using Super-Solder
     Y. Obara, H. Irie and K. Fuse, Super Solder Technologies
     H. Shiroishi, Furukawa Electric; Y. Nishi, Harima Chemicals, Japan

6.4  Frame Wirebonding
     J. W. Balde, IEEE CHMT Standard Chair, USA
     J. Walker, Northern Telecom, Canada
Session 7:  Material and Applications  (Wednesday, Dec. 2, 1992, 8:00-10:05)
  Co-Chairs:  Karel Kurzweil, Bull and Nobuo Kamehara, Fujitsu

7.1  Development and Commercializing of Ionic Type Photosensitive Polyimides
     M. Asano, M. Eguchi, K. Kusano and K. Niwa, Toray Industries, Japan

7.2  Via Generation in Benzlycyclobutane Dielectrics
     D. C. Fryel, R. F. Harris, R. H. Heistand II, E. S. Moyer, E. S. Rutter and P. Garrou, Dow Chemical, USA
     M. J. Berry, B. Rogers and I. Turlik, MCNC, USA
     S. Bidstrup, T. Hodges, P. Kohl and J. Taylor, Georgia Inst, of Tech., USA
     K. Berry, F. David and M. Lanka, Polyoon, USA

7.3  A Thermal Stable Water Soluble Solder Paste
     B. Carpenter, K. Pcarsall, R. Raines and R. Reich, IBM, USA

7.4  Development and Applications of High Reliable Cofired Aluminum Nitride Packages
     N. Ito and R. Imura, Kyocera, Japan

7.5  Multilayer AlN Circuit Board for VLSI Packaging
     M. Hida, M. Tsukada, K. Hashimoto and N. Kamehara, Fujitsu Lab., Japan
Session 8:  MCMs  (Wednesday, Dec. 2, 1992, 10:35-13:00)
  Co-Chairs:  John W. Balde, IDC and Hisashi Tomimuro, NTT

8.1  Coaxial SMT Module Connector for High-speed MCM
     S. Sasaki, T. Kishimoto and N. Sugiura, NTT, Japan

8.2  Flip Chip, Multichip Modules, Microsystem Applications
     G. Nicolas, LETI-DTA, France

8.3  High Frequency Properties of Multi Chip Modules
     Hans Hentzell, IMM, Sweden

8.4  High Density Si on Module
     M. Kimura, T. Shimoto, K. Matsui, T. Kusaka, N. Senba and T. Koike, NEC, Japan

8.5  A Flip Chip Interconnection with Solid Copper Core Technology for Multichip Modules
     K. Suzuki, H. Uchida, A. Haga and K. Suzuki, NEC, Japan

8.6  A Comparison of MCM Implementations for Mainframe and Workstation Computers
     K. K. Liu and S. Westbrook, MicroModule Systems, Inc., USA
Closing Remarks  (Wednesday, Dec. 2, 1992, 13:00)