2nd Workshop Technical Program
(Nov. 30-Dec. 2, 1994)

Welcome and Invited Paper Session  (Wednesday, Nov. 30, 1994, 9:00-10:00)
  Chair:  T, Sudo, Toshiba

1.  High Performance Low Cost Microprocessor Packaging
    B. Siu, Intel Corp.

2.  TCPs for High-Density LCD Mounting
    M. Kada, Sharp Corp.
Session 1:  Materials and Package Compound  (Wednesday, Nov. 30, 1994, 10:00-12:00)
  Co-Chairs:  K. Kurzweil, Bull and N. Kamehara, Fujitsu

1.1  A Molding Compound for Surface Mounted Devices
     Y. Takigawa, S. Yagi and Y. Nakata, Fujitsu Laboratories Ltd

1.2  Low Cost Epoxy Resin for IC Molding Compound Applicable for SMD
     I. Ogura and K. Takahashi, Dainippon Ink & Chemicals, Inc.

1.3  Molding Compound Operating Life after High Temperature Aging Relationship among Au-Al Bonding Reliability, Molding Compound and Impurity on Al Pad Surface
     Y. Uchida, Y. Shizuno and Y. Kohara, Oki Electric Industry
Session 2:  Electrical Modeling and Simulation  (Wednesday, Nov. 30, 1994, 13:00-15:00)
  Co-Chairs:  J. I. Kim, Anam and E. J. Rymaszewski, RPI

2.1  Signal Transmission on Leads of TAB-BGA Package
     T. Kumakura, T. Sugiyama, S. Sinzawa and M. Mita, Hitachi Cable Ltd.

2.2  High Frequency Characterization of Chip Contacting Options by Full Wave Simulation Technique
     S. Cyrusian, Technical University of Berlin

2.3  A Novel Millimeter-Wave IC on Si Substrate Using MBB Technology
     T. Yoshida, K. Hatada, H. Sakai, Y. Ota, K. Inoue, K. Takahashi, S. Fujita and M. Sagawa, Matsushita Electric Industrial Co., Ltd.

2.4  A New Compact Coaxial Feedthrough Package for Wideband IC Modules
     N. Kukutsu, M. Hosoya and N. Sato, NTT
Session 3:  Single Chip Packaging for High Density  (Wednesday, Nov. 30, 1994, 15:30-18:30)
  Co-Chairs:  A. W. Lin, ITRI and K. Hatada, Matsushita

3.1  A New Thermal Solution with a Standard Plastic Package
     S. Lee, N. Kwak, J. Yoon, C. Kwak and W. Shin, Anam Industrial Co., Ltd.

3.2  Smallest Flip-Chip-Like Package "Chip Scale Package (CSP)"
     M. Matsuo, S. Baba, H. Matsushita, T. Satou, M. Yasunaga, S. Nakao and T. Tachikawa, Mitsubishi Electric Corp.

3.3  CSP (Chip Size Package)
     Y. Kunitomo, Y. Sakashita, M. Nozu, S. Kageyama, A. Yamamoto, A. Saito and K. Ishikawa, Matsushita Electronics Corp.
     T. Ishida, Y. Nakamura and T. Matsuo, Matsushita Electric Industrial Co, Ltd.

3.4  Thin Wirebonded Exposed-Die Molded Package
     W. R. Hamburgen and J. S. Fitch, DEC

3.5  A Plastic Cavity Down Ball Grid Array for High-Speed High-Power Devices
     K. Kaizu, T. Kishimoto and S. Sasaki, NTT

3.6  High-Speed and Compact Compact Pin-Grid-Array Package for MCMs
     S. Yamaguchi, H. Tomimuro and Y. Ohno, NTT
Session 4:  Electromagnetic Simulation (1)  (Thursday, Dec. 1, 1994, 8:00-9:30)
  Co-Chairs:  T. B. Lim, National Univ. of Singapore and H. Reichl, Tech. Univ. Berlin

4.1  A Simultaneous Switching Noise Design Algorithm for Leadframe Packages
     C. Huang, Y. Yang and L. Prince, University of Arizona

4.2  Switching Noise in High Speed Digital Systems
     S. Gong and H. Hentzell, Industrial Microelectronics Center

4.3  Inductance Measurement of Sub-Nano Henry Order Using a Zero Parasitic Inductance Probe System
     T. Nagata, H. Shimizu and A. Nakamura, Hitachi Ltd.
Session 5:  Fine Manufacturing Process  (Thursday, Dec. 1, 1994, 10:00-12:00)
  Co-Chairs:  D. R. Olsen, Motorola and T. Ohde, Sony

5.1  Research on Ultra-Fine Pitch Leadframe Manufacturing Process (UFPL)
     K. Ohsawa, M. Itoh, M. Nagano, H. Takahashi, T. Seki and A. Kojima, Sony Corp.

5.2  Fluxless Soldering with a Laser for Assembly of Tape Carrier Package
     A. Adachi, K. Murakami, Y. Morihiro and S. Hoshinouchi, Mitsubishi Electric Corp.

5.3  Surface Treatment Method to Polyimide Buffer Coat and Its Affection to Adhesion-Delamination on Chip Surface after Reflow Soldering
     N. Murakami, Y. Shizuno and Y. Kohara, Oki Electric Industry

5.4  Evaluation of Fine Pad Pitch Wire Bonding
     I. S. Yoon, Anam Industrial Co., Ltd.
Luncheon Session  (Thursday, Dec. 1, 1994, 13:00-13:30)
  Chair:  H. Shibata, Mitsubishi

1.  CHIPPAC: A European Packaging Project
     K. Kurzweil, Bull SA
Session 6:  Multi-Chip Module (1)  (Thursday, Dec. 1, 1994, 13:30-15:00)
  Co-Chairs:  Eugene J. Rymaszewski, RPI, USA and H. Tomimuro, NTT

6.1  Small Planar Packaging System for High-Throughput Switching Systems
     T. Kishimoto, K. Yasuda, H. Oka, S. Sasaki, A. Harada and Y. Kaneko, NTT

6.2  MCM in the Telecommunication Environment
     R. De Bondt, K. Allaert, J. Cannaerts and A. Ackaert, Alcatel Bell Telephone

6.3  A New Method to Produce Cost-Effective Known Good Die
     I. Ung Kim, S. H. Lee and J. M. Park, Samsung Electronics Co., Ltd.
Session 7:  Electromagnetic Simulation (2)  (Thursday, Dec. 1, 1994, 15:30-17:00)
  Co-Chairs:  H. Henzell, Linkoping University and A. Nakamura, Hitachi

7.1  Characterization of Ground Plane Inductance in Traces on Sheet Conductor System
     H. Shimizu, T. Nagata and A. Nakamura, Hitachi Ltd.

7.2  SPICE Modeling of Power and Ground Planes by Partial Element Equivalent Circuit Method
     M. Kabumoto, H. Wada, H. Okamoto, S. Ninomiya, K. Nakamura and M. Nishimura, Kyocera Corp.

7.3  Modeling and Analysis of Multichip Module Power Supply Planes
     K. Lee and A. Barber, Hewlett-Packard Laboratories
Session 8:  Thermo-Mechanical Stress Simulation  (Friday, Dec. 2, 1994, 8:00-10:00)
  Co-Chairs:  E. D. Pope, Intel and Y. Kohara, Oki

8.1  Thermal Fatigue Life of Eutectic Solder Bumps for Flip Chip Interconnection
     K. Doi, N. Hirano, M. Mukai, T. Okada, Y. Hiruta and T. Sudo, Toshiba Corp.

8.2  Computer Simulation Designs for Lead-On-Chip Packages
     M. Amagai, Texas Instruments Japan

8.3  Strength Design for Thin Body IC Ceramic Packages Using FEM Analysis
     M. Ishibashi, J. Fujimoto, S. Morishige and K. Kaneda, NEC Corp.

8.4  Linear Finite Element Stress Simulation of Solder Joints on the 255 I/O's Plastic BGA Package under Thermal Cycling
     R. Shen Lee, J. Yu Lee and T. H. Ho, ITRI
Session 9:  Reliability  (Friday, Dec. 2, 1994, 10:30-12:30)
  Co-Chairs:  G. G. Harman, NIST and N. Chandler, GEC Marconi

9.1  Improvement in TSOP Solder Joint Reliability Using Low CTE PCB
     R. Kimoto, H. Kawakubo, K. Otsuka, Y. Kojima, M. Kitano and M. Noda, Hitachi Microcomputer System Ltd.

9.2  Lead/Tin (95/5 wt.%) Bumping - A Comparison of Different Technologies
     J. Wolf, G. Chmiel, J. Simon, D. Krabe and H. Reichl, Technical University of Berlin

9.3  Thermal Characterization of Resin Die-Bond Defects for VLSI Packages
     Y. Yamaji, Y. Tsuboi, O. Yamagata, H. Nakayoshi, M. Nii and T. Sudo, Toshiba Corp.

9.4  Estimation of Thermal Cycle (T/C) Life-Time for Resin Mold Packages
     Y. Kaga, T. Saito, J. Fujimoto and T. Uno, NEC Corp.
Session 10:  Multi-Chip Module (2)  (Friday, Dec. 2, 1994, 13:30-15:30)
  Co-Chairs:  I. Turlik, MCNC and T. Kusaka, NEC

10.1  A Multi-Chip Module with Thin-Film and Thick-Film Capacitors
     S. Sasaki and T. Kishimoto, NTT

10.2  Cu/Photosensitive-BCB MCM-D Technology for Advanced Applications
     T. Shimoto, K. Matsui and K. Utsumi, NEC Corp.

10.3  High Performance Plastic Molded Multichip Module
     T. Ozawa, H. Sorimachi, M. Takeuchi and T. Otsuka, Fujitsu Ltd.

10.4  Development of Low-Cost Three-Dimensional Package
     S. Ho Ahn, Samsung Electronics Co.
Closing Remarks  (Friday, Dec. 2, 1994, 15:30)