3rd Workshop Technical Program
(Dec. 2-4, 1996)

Welcome and Invited Papers  (Monday, Dec. 2, 1996, 9:00-10:30)
  Chair:  K. Otsuka

1.  Opening remarks
    T. Sudo, Toshiba Corp.

2.  Trend of Advanced Circuits Manufacturing Technology
    Osamu Yamazaki, Matsushita Electric Industrial

3.  The Interconnected Mesh Power System (IMPS) MCM Topology and Applications
    Leonard Schaper, Univ. of Arkansas, U.S.A.
Session 1:  Assembly Process  (Monday, Dec. 2, 1996, 10:30-12:00)
  Co-Chairs:  Y. Kohara and S. Liu

1.1  New Wire Bonding Technology for Fine Pad Pitch
     H. Horibe, K. Nakamura and T. Akiyama, Mitsubishi Electric Corp.

1.2  Development of Plastic QFP with Small Die-Pad Configuration
     Y. Miyaki, H. Suzuki and K. Tsubosaki, Hitachi, Ltd.
     Y. Kajiwara, K. Suzuki, A. Kameoka and F. Ito, Hitachi Microcomputer System Ltd.

1.3  High-Performance and Low-Cost Molding Compound for SMD
     S. Yokoi, M. Yukawa, K. Mogami, T. Terasaki and T. Ohde, Sony Corp.

Session 2:  Electrical Modeling and Simulation  (Monday, Dec. 2, 1996, 13:30-15:30)
  Co-Chairs:  A. Nakamura and J. Prince

2.1  An Accurate and Effective Method for Simultaneous Switching Noise Simulation Using Effective Inductance for Thin Film Packages
     C. Huang and John L. Prince, University of Arizona, USA

2.2  Electrical Characterization of Thin-film Wiring using Meshed Ground
     A. Owzar, M. Kasper, M. Topper, O. Ehrmann and H. Reichl, Technical Univ. of Berlin
     J. Wolf and K. Buschick, FhG IZM Berlin, Germany

2.3  Inductance Calculation and Circuit Analysis of Multiple Arbitrary Shaped Planes
     A. Yokomori, H. Fukumoto, T. Nagata, H. Shimizu and A. Nakamura, Hitachi, Ltd.

2.4  Noise Simulation of AlN LGA Package with Ground and Power Planes Formed Under a Chip
     K. Yano, J. Kudo, H. Asai, N. Iwase and M. Endo, Toshiba Corp.

Session 3:  Flip-Chip Interconnection  (Monday, Dec. 2, 1996, 16:00-18:00)
  Co-Chairs:  H. Shibata and B. Hamburgen

3.1  Flip Chip and Assembly Evolutions from VLSI to Microsystems
     G. Nicolas, C. Massit and P. Caillat, CEA-LETI, France

3.2  Solder Immersion Bumping Technology for Flip Chip
     J-H. Song, S-M. Seo and Y-W. Heo, Anam Industrial, Co., Ltd., Korea

3.3  Low Cost Flip Chip Interconnection Method: the Resin Press Contact Technology
     T. Murakami, R. Yoshino and T. Shimada, NEC Corp.

3.4  An Infrastructure for the Sourcing of Die at the Required Level of Goodness
     M. G. Roughton, Lucas Ltd., UK
Session 4:  Package Reliability  (Tuesday, Dec. 3, 1996, 8:00-10:00)
  Co-Chairs:  K. Hirata and G. Harman

4.1  The Effect of Cu Leadframe Oxidation on the Cu/EMC Adhesion
     S-J. Cho and K-W. Paik, Korea Advanced Institute of Science and Engineering (KAIST), Korea

4.2  The Effect of Copper Leadframe Oxidation on Package Crack and Delamination
     E. Takano, K. Takahashi and S. Shimizu, Toshiba Corp.

4.3  The Influence of Molding Compound on the Au-Al Bond Reliability under High Temperature
     Y. Tanaka, Y. Uchida, Y. Shizuno and Y. Kohara, Oki Electric Industry Co., Ltd.

4.4  Influence of Packaging Materials on BGA/microBGA Reliability
     K. Abe, Y. Nagasawa and S. Wakabayashi, Shinko Electric Industries Co., Ltd.
Session 5:  Chip Scale Packages(Tuesday, Dec. 3, 1996, 10:30-12:30)
  Co-Chairs:  K. Furuya and G. Nicolas

5.1  Development of Bump Chip Carrier (BBC)
     Y. Yoneda, Fujitsu Ltd.

5.2  Development of Chip Scale Package using Flex Substrate
     T. Ohuchida, K. Murata, M. Watanabe and K. Ano, Texas Instruments Japan

5.3  Chip-on-Frex Technology for Chip Scale Implementations
     M. Christforo, D. H. Reep, W. R. Kritzler and P. Bronecke, Lockheed-Martin, USA
     R. A. Fillion and K. Kolc, General Electric, USA

5.4  A Computational Comparison of Different CSP Approaches
     J. Simon, J. Auersperg and H. Reichl, Technical Univ. of Berlin, Germany
     A. Schubert, FhG IZM Berlin, Germany
Session 6:  Conductive Adhesives and Materials  (Tuesday, Dec. 3, 1996, 14:30-16:30)
  Co-Chairs:  N. Kamehara and H. W. Lee

6.1  High Frequency Characterization of Conductive Adhesive
     K. Otsuka, Meisei Univ.
     I. Watanabe and K. Takemura, Hitachi Chemical Co. Ltd.

6.2  Interconnection Characteristics of Anisotropic Conductive Paste
     Y. Kishimoto, H. Hashimoto and K. Nishimura, Toshiba Chemical Corp.

6.3  Co-Fired Metallization of PNN-PT-PZ Piezoelectric Ceramics to Ag/Pd Conductor
     N. Kamehara, Y. Imanuka, M. Hida, M. Tsukada and K. Kurihara, Fujitsu Lab. Ltd.

6.4  Wideband Permitivity Modeling of FR-4 Composites in a Wide Range of Composition Ratios
     J. K. Hong, LG Info & Comm Ltd.
     S. I. Kim, H. Y. Lee and J. K. Hong, Ajou Univ., Korea
Session 7:  Thermal/Mechanical Simulation and Evaluation  (Tuesday, Dec. 3, 1996, 17:00-19:00)
  Co-Chairs:  T. Mimura and K. W. Paik

7.1  Nonlinear FE-Simulation for Packaging Applications
     R. Dudek, R. Doring and B. Michel, FhG IZM Berlin, Germany

7.2  Thermal Fatigue Analysis for Solder Bump in BGA Package
     K. Iwasaki, M. Mukai and M. Ikemizu, Toshiba Corp.

7.3  High-Temperature Deformation of Area Array Packages by Moire Interferometry / FEM Hybrid Method
     D. Zhu, D. Zou, F. Dai and S. Liu, Wayne State Univ., USA
     Y. F. Gue, Motorola Semiconductor Products, USA

7.4  A Unified Multi-Axial Sub-micron Fatigue Tester for Miniaturized Specimens
     M. Liu and S. Liu, Wayne State Univ., USA
Session 8:  High Frequency Characterization and Modeling  (Wednesday, Dec. 4, 1996, 8:00-10:00)
  Co-Chairs:  F. Ishitsuka and J. Balde

8.1  Double Bonding Wires Buried in a Dielectric Material for Minimizing the Parasitic Effects
     S. J. Kim, Sang-Don Lee and Hai-Young Lee, Ajou Univ., Korea

8.2  AlN Ceramic Package for a High-Speed Parallel Optical Link Module
     N. Tanaka, Y. Arai, Y. Ohno and H. Takahara, NTT Corp.

8.3  High Frequency Characteristics of Transmission Line Using Via Method
     T. Miyamoto, K. Nagata and F. Miyagawa, Shinko Electric Industries Co., Ltd.

8.4  Full-Wave Simulation of High Speed Digital Packages
     P. Pyzowski, Ansoft Corp. Japan Branch; M. Tomita, Innotech. Corp.
Session 9:  MCM and High-Speed Systems  (Wednesday, Dec. 4, 1996, 10:30-12:30)
  Co-Chairs:  H. Tomimuro and L. Schaper

9.1  3-Dimensional Memory Module Assembly Technology
     H. Kusamitsu, K. Tokuno, I. Morisaki, N. Senba and N. Takahashi, NEC Corp.

9.2  High-Speed/High-Frequency Digital MCMs -A Case Study-
     C. Truzzi, E. Beyne and E. Ringoot, IMEC, Belgium

9.3  High-Frequency Performance of a Novel RF Interconnection System with Miniaturized In-line Coaxial Connectors
     F. Ishitsuka, N. Iwasaki, Y. Ando, N. Kukutsu and T. Ohira, NTT Corp.

9.4  High-Speed Signal Transmission at the front of a Bookshelf Packaging System
     S. Koike, T. Kishimoto and K. Kaizu, NTT Corp.
Session 10:  Ball Grid Array Packages  (Wednesday, Dec. 4, 1996, 13:30-16:00)
  Co-Chairs:  T. Ohde and D. Olsen

10.1  Patent Briefing on a Method for Testing BGA components
      S. Gong, H. Hentzell and P. Bodo, IMC, Sweden

10.2  Development of TBGA using Ultra-Fine Pitch Leadframe (UFPL)
      K. Sato, K. Ohsawa and T. Ohde, Sony Corp.

10.3  High Performance Cavity-down Metal Based BGA (MeBGA) Package
      K. Suzuki, H. Uchida, K. Shibuya and A. Haga, NEC Corp.

10.4  Flip-TAB Ball Grid Array Package Development
      S. Yamada, K. Harada, H. Tsutsumi, M. Watanabe, T. Hashimoto, N. Ueda and K. Nakagawa, Mitsubishi Electric Corp.

10.5  C-BGA Package using Film Intaglio Transfer (FIT) Printing Technology
      H. Matsunaga, Matsushita Electronic Components Co., Ltd.
Closing Remarks  (Wednesday, Dec. 4, 1996, 16:00)