4th Workshop Technical Program
(Nov. 30-Dec. 2, 1998)
Welcome and Invited Papers (Monday, Nov. 30, 1998, 10:00-12:00)
Chair: K. Otsuka
1. Opening Remarks
Nobuo Kamehara, Fujitsu
2. Thermo-Mechanical Characterization in Electronic Packaging Materials
and Structures
Sheng.Liu, Wayne state Univ.
3. Trends of Technology and Application for Low Temperature Co Firable
Ceramics
K. Inagaki, SMI
4. Trends of Sony Mounting Technology for Portable consumer Products
K. Iwabuchi, Sony
Session 1: Chip Scale Packages / Bare Chip Packaging (1) (Monday, Nov. 30, 1998, 13:00-15:00)
Co-Chairs: Y. Okada and S. Mizumoto
1.1 Flip-chip CSP using A Double Layered ALIVH Substrate
T. Tomura, S. Yuhaku, M. Itagaki, Y. Bessho, K. Eda,
M. Tsukamoto and T.Ishida, Matsushita Electric
1.2 High Quality Small Package Development by Flip Chip Method
Y. Egawa, Y. Shiraishi, S. Ohuchi and Y. Kohara, Oki
Electric Industry
1.3 A Flip-chip BGA with Organic Substrate for High Performance Devices
M. Watanabe, S. Baba, Y. Tomita, H. Matsushima, E.
Hayashi, M. Namatame and Y. Takemoto, Mitsubishi
1.4 A Robust and Low Cost Stack Chips Package
D. H. Kim, S. J. CHO, M. G. Park, H. G. Paik and Y.
H. Choi, Soonjin CHO, Hyundai Electronics, Korea
Session 2: Electrical Characterization (1) (Monday, Nov. 30, 1998, 15:30-17:00)
Co-Chairs: L. Schaper and F. Ishitsuka
2.1 Reduced Parasitic Inductance in µBGA Package Using Floating
Conductive Plane
M. Kobayashi, H. Murakami, T. Yasuda and T. Kumakura,
Hitachi Cable, Ltd.
2.2 An Algorithm for Sensitivity Analysis of Electrical Performance
Parameters
C. Jiao, J. L. Prince, A. Yaghmour and A. C. Cangellaris,
University of Arizona, University of Illinois, USA
2.3 Signal Line Electrical Characterization in a Build-Up Printed
Circuit Board
K.Yamanaka and Y.Tsukada, IBM Japan
2.4 A High-Effective PCB Simulator Including IC Characteristics
H. Kimura, NTT
Session 3: Packaging Trend (Tuesday, Dec. 1, 1998, 8:50-10:30)
Chair: Y. Hirata
3.1 Worldwide Market Trends in Area Array Packaging
E. Jan Vardaman, TechSearch International
3.2 US SIA Packaging Roadmap and Challenged
R. Werner and C.S. Chang, SEMATECH Inc.
3.3 Recent Activity and Progress in the Institute for Advanced Micro-System
Integration
K.Otsuka, Meisei University
Session 4: Electrical Characterization (2) (Tuesday, Dec. 1, 1998, 10:30-12:30)
Co-Chairs: T. Sudo and J. Prince
4.1 A New RLC Modeling Tool Based on the Partial Element Equivalent
Circuit (PEEC) Technique
S. Hasan, A. Cangellaris and J. Prince, Univ of Arizona,
USA
4.2 Relationship between Radiated Emissions and Voltage Fluctuation
Caused by LSI
S. Shirakawa, H. Fukumoto, A. Nakamura, M. Katagiri,
T. Hayashi, G.Yokomizo, S. Otake, H. Shimizu, K. Shinbo and T. Suga, Hitachi
Ltd.
4.3 Signal Propagation on Seamless High Off-Chip Connectivity (SHOCC)
Interconnects
L. W. Schaper, S. Afonso, W. D. Brown and J. P. Parkerson,
University of Arkansas, USA
4.4 Compact Liquid-Cooling System for High-Speed Switching MCMs
K. Okazaki, N. Yamanaka, A. Harada, S. Sasaki and T.
Kishimoto, NTT
Panel Discussion: Electrical Performance Required for Future Packaging
Materials (Tuesday, Dec. 1, 1998, 13:30-15:00)
Chair: A. Nakamura
Panelists: T. Sudo, F. Ishitsuka, L. Schaper, J. Prince and
K. Otsuka
Session 5: Reliability (Tuesday, Dec. 1, 1998, 15:30-17:30)
Co-Chairs: Y. Kohara and S. Liu
5.1 Evaluation of Barrier Metals of Sn-Ag Solder Bumps for Flip-Chip
Interconnection
S. Honma, M. Miyata, H. Aoki and Y. Hiruta, Toshiba
Corp.
5.2 Progressive Deformation in BGA Solder Bumps under Thermal Cycle
Loads
T. Kawakami, H. Takahashi, M. Mukai and K. Takahashi,
Toshiba Corp.
5.3 High Resolution Deformation Measurement on CSP and Flip Chip
Dietmar Vogel, Jurgen Simon, Andreas Schubert and Bernd
Michel, Fraunhofer Institute of Reliability and Microintegration, IZM,
Germany
Session 6: Materials (1) (Tuesday, Dec. 1, 1998, 18:00-19:30)
Co-Chairs: M. Kohno and J. Harman
6.1 Thin Film Polymeric Materials in Microelectric Packaging and
Interconnect: An Overview
P. Garrou, Dow Chemical, USA
6.2 Development of Novel Anisotropic Conductive Film
F. Eriguch, Y. Hotta, M. Yamaguchi, M. Maeda and F.
Asai, Nitto Denko Corp.
6.3 Anisotropic Conductive Paste (ACP) Available for Flip Chip
Minoru Hara, Toshiba Chemical Co.
Session 7: Materials (2) (Wednesday, Dec. 2, 1998, 8:50-10:40)
Co-Chairs: N. Kamehara and P. Garrou
7.1 Development of a Bumped Tape Carrier (BTC) for CSP Substrate
T. Asada and T. Amano, Furukawa Electric Industry Corp.
7.2 High-Density Build-Up Packaging Substrate for High-Pin-Count
Area Array Interconnections
T. Shimoto, K. Matsui, Y. Shimada and K. Utsumi, NEC
7.3 An Adhesive for Tapa Ball Grid Array Packages
Y. Takigawa and E. Yano, Fujitsu Ltd.
Session 8: Chip Scale Packages / Bare Chip Packaging (2) (Wednesday, Dec. 2, 1998, 10:40-12:30)
Co-Chairs: T. Mimura and J. Vardaman
8.1 Development of MITSUBISHI Mold CSP
S. Yamada, M. Yasunaga, K. Harada, Y. Takemoto, K.
Misumi, Y. Takata, A. Yamazaki, A. Sawai, M. Hisahara, K. Imamura, Y. Noguchi
and Y. Hirata, Mitsubishi Electric Corp.
8.2 Development of Real Chip Size Package Using the Wafer Level Assembly
Process
N. Murakami, H. Kikuchi, S. Ohuchi, T. Ohsumi and H.
Kobayashi, Oki Electric Industry Co.
8.3 Development of SMAAP (Super Mold Area Array Package)
M. Suwa, M. Onodera, S. Nakaseko and T. Kawahara, Fujitsu
Ltd.
Closing Remarks (Wednesday, Dec. 2, 1998, 12:30)