6th Workshop Technical Program
(Nov. 12-14, 2002)
Tuesday, November 12th, 2002
9:50-10:30 Welcome & Invited Talks Chair: Kanji Otsuka, Meisei Univ.
1. Opening Remarks
Atsushi Nakamura, Hitachi, Ltd.
2. Microprocessor Packaging Challenges in Power Management
Raj Nair, Intel Corp.
10:30-12:00 Session 1: Printed Circuit Board Chair: Kimihiro Yamanaka
1.1. Development of the Novel Interconnection Technology for Multilayer
Substrate
Ryoichi Okada, Sumitomo Bakelite Co., Ltd.
1.2. Novel Laser Micro-Via Organic Substrate Technology for Semiconductor
Package
Hiroyuki Mori, Kaoru Kobayashi, Kimihiro Yamanaka,
and Yutaka Tsukada, IBM Japan
1.3. Development of Industrial Scale Manufacturing Line for Integrated
Module Board Technology
Risto Tuominen and Petteri Palm, N.N., Imbera Electronics
Oy, Finland
13:00-15:30 Session 2: Interconnects and New Packages Co-Chairs: Yasufumi Uchida and Tadaaki Mimura
2.1. Development of Adhesive Enabling Replacement of Bare Chips on PWB
Hideshi Tokuhira, Tomohisa Yagi, Hiroaki Date, and
Eiji Horikoshi, Fujitsu Laboratories Ltd.
2.2. Wire Bonding Analysis and Yield Improvements for Cu Low-K IMD Chip
Packaging
Tai-Chun Huang, Ming-Shouh Liang, Tze-Liang Lee, Shin-Chang
Chen, Douglas C.H. Yu, and Mong-Song Liang, Taiwan Semiconductor Manufacturing
Company, Taiwan
2.3. Development of System-in-a-Package Utilizing Ultrasonic Flip-Chip
Bonding Technologies
Toshihiro Iwasaki, Keiichiro Wakamiya, Tatsuo Nishihara,
Yoshihiro Tomita, Yasumichi Hatanaka, and Michitaka Kimura, Mitsubishi
Electric Corp.
2.4. Development of MCP Incorporating a Highly Reliable Wafer-Level Chip
Size Package
Yoshimi Egawa, Oki Electric Industry Co., Ltd.
2.5. High-Density, Fine-Pitch CSP Based on Multi-Layer Thin Substrate Technology
Katsumi Kikuchi, Tadanori Shimoto, Wataru Urano, Hironori
Ohta, Keiichiro Kata, and Kazuhiro Baba, NEC Corp.
16:00-18:00 Session 3: Process Co-Chairs: Michitaka Kimura and George Harman
3.1. Process Control of the Reflow of AuSn Bumps
M. Hutter, H. Oppermann, G. Engelmann, J. Wolf, O.
Ehrmann, R. Aschenbrenner, and H. Reichl, Fraunhofer IZM-Berlin, Germany
3.2. Development of the High-Density Multilayer Wiring Package Process
Using a Photosensitive Polyimide
Katsuya Kikuchi, Shigemasa Segawa, Eun-Sil Jung, Hiroshi
Nakagawa, Kazuhiko Tokoro, Hiroshi Itatani, and Masahiro Aoyagi, National
Institute of Advanced Industrial Science and Technology (AIST)
3.3. Innovative Material Deposition Technologies Using New Machine Concepts
Wafer Bumping
J. Kloeser, O. Dinse, J. Schmdt, R. Heynen, and B.
Lemmermeyer*, EKRA Eduard Kraft GmbH Maschinenfabrik, *Fachhochschule Heilbronn,
Germany
3.4. Probe Mark Effect on Fine Pitch Wirebonding
Hiromitsu Miyai, IBM Japan
Wednesday, November 13th, 2002
9:00-10:30 Session 4: Solder Joint Chair: Tomoshi Ohde
4.1. A Study in Flip-Chip UBM/Bump Reliability with Effects of Sn-Pb Solder
Composition
Jenq-Dah Wu, Advanced Semiconductor Engineering, Inc.,
Taiwan
4.2. Evaluation Method of the Impact Shear Strength for the Solder Bump
Bonded Interface in Semiconductor Encapsulation
Toshiaki Morita, Hitachi, Ltd.
4.3. Environmental Impacts of Electronic Packaging Materials
Nobuo Kamehara, N. F. Cooray, Hiroaki Date, Masayuki
Ochiai, and Eiji Horikoshi, Fujitsu Laboratories Ltd.
10:45-12:45 Session 5: RF & Optoelectronics Co-Chairs: Noboru Iwasaki and Phillip Garrou
5.1. Characteristics GaAs HEMTs with Flip-Chip Interconnection Structure
Using Underfill Resin
Yuji Iseki and Naoko Ono, Toshiba Corp.
5.2. Multi-chip BGA Package with the Connectors for 40Gb/s MUX/DMUX Chipset
Hideko Ando, Hiroshi Kikuchi, Satoru Isomura, and Norio
Nakazato, Hitachi, Ltd.
5.3. Development of an Optical Active Connector for LAN
Nobuyuki Tanaka, Yukio Komine, Noboru Iwasaki, and
Yoshimitsu Arai, NTT Microsystem Integration Laboratories
5.4. Inter-Chip Optical Interconnection Using Optoelectronic Integration
and Diffractive Optics
Takeshi Takamori, Hironori Sasaki, and Hiroshi Wada,
Oki Electric Industry Co., Ltd.
13:45-15:45 Session 6: Electrical Design (1) Co-Chairs: Toshio Sudo and Len Schaper
6.1. Development of a Non-Contact Current Distribution Measurement Technique
for LSI Packaging on PCBs
Kouichi Uesaka, Kenichi Shinbo and Takashi Suga, Hitachi,
Ltd.
6.2. Improvement of the Transmission Characteristic by the Embedded Transmission
Line
Yasuhiko Odate, *Chihiro Ueda, **Eiji Tanabe, *Kanji
Otsuka, and Tadatomo Suga, Univ. of Tokyo, *Meisei Univ., **AET Japan Inc.
6.3. EMI Reducing Techniques for Low Voltage Differential Signaling on
a Flexible Printed Circuit Board
Ayako Takagi and Haruhiko Okumura, Toshiba Corp.
6.4. 10GHz Electrical Characterization and Limit of Organic BGA Packages
With and Without Plating Stub
Chih-Pin Hung, Advanced Semiconductor Engineering,
Inc., Taiwan
16:15-17:45 Session 7: Materials Chair: Masahiko Kohno
7.1. Study of Integrated Passive Components
Masahiko Ogino, Hitachi, Ltd.
7.2. Polymer Integrated Circuits Based on Polyfluorene Derivatives
Mitchell Dibbs and Phillip Garrou, Dow Chemical-Advanced
Electronic Materials, USA
7.3. Development of Assembly Technology for High Reliability Flip Chip
Package
Satoru Katsurayama and Hiroshi Watabe*, Sumitomo Bakelite
Co., Ltd., *Toshiba Corp.
18:15-19:45 Session 8: Trends Chair: Fuminori Ishitsuka
8.1. Optoelectronic Manufacturing Trends in China
E. Jan Vardaman and Timothy J. Urekew, TechSearch International,
Inc., USA
8.2. Advances in 3D Packaging - Trends and Technologies for Multi-chip
Die and Stacking
Lee Smith, Y.W. Heo and Akito Yoshida, Amkor Technology,
Inc., USA
8.3. Advanced Semiconductor Packaging Solutions: CSP to SiP
Ann Marie Pate, Tessera Technologies, USA
Thursday, November 14th, 2002
9:00-10:30 Session 9: Electrical Design (2) Chair: Kunihiko Nishi
9.1. Replacement of Bypass Capacitor to Transmission Line for High Frequency
Power Supply System
Keisuke Saito, Yutaka Akiyama*, Tamotsu Usami, Kanji
Otsuka*, and Tadatomo Suga, University of Tokyo, *Meisei University
9.2. Simultaneous, Switching Noise of Wafer Level Packaging - BGA for SRAM
Yutaka Uematsu, Hideki Osaka, Naoto Taoka, and Motoo
Suwa, Hitachi, Ltd.
9.3. Usefully Smart Power Supply Circuit
Chihiro Ueda, Yutaka Akiyama*, Kanji Otsuka*, Tamotsu
Usami**, Yasuhiko Odate**, and Keisuke Saito**, AET Japan Inc., *Meisei
University, **University of Tokyo
10:45-12:45 Session 10: 3D Packaging & Wafer level CSPs Co-Chairs: Nobuo Kamehara and E. Jan Vardaman
10.1. Enabling Advanced VLSI Architectures Using Through-Silicon Via 3D
Layer Stack Technology
Leonard W. Schaper and Silke A. Spiesshoefer, University
of Arkansas/HiDEC, USA
10.2. 3D-Integration of Integrated Circuits by Interchip Vias (ICV) and
Cu/Sn Solid Liquid Interdiffusion (SOLID)
P. Ramm, A. Kiumpp, and R. Wieland, Fraunhofer Institute
IZM, Germany
10.3. Chip Size Module, The Ultra High Integrated Module, Evolved from
Wafer Level Packaging
Masamitsu Ikumo, Yoshitaka Abe, Osamu Igawa, Tetsuya
Fujisawa, Hirohisa Matsuki, and Mitsutaka Sato, Fujitsu Ltd.
10.4. Superfine Flip-Chip Bonding Technologies for 3D Stacked System-in-a-Package
Utilizing Tin-Capped Cu Bumps in 20µm-pitch
Masamoto Tago, Yoshihiro Tomita, Yoshihiko Nemoto,
Kazumasa Tanida, Mitsuo Umemoto, and Kenji Takahashi, Association of Super-Advanced
Electronics Technologies (ASET)
13:45-15:45 Session 11: Topics Co-Chairs: Atsushi Nakamura and Hirofumi Nakajima
11.1. Impacts of the Assembly Process to the Cu/LK IMD Chip Integrity
Ming-Shuoh Liang, Taiwan Semiconductor Manufacturing
Company, Taiwan
11.2. Integrated CCD Micro-Camera System Module for Visual Inspection Realized
by High-Density 3D Microsystem-in-Package Technology
Hiroshi Yamada, Takashi Togasaki, Atsushi Sadamoto,
and Halide Sudo, Toshiba Corp.
11.3. A Full-Wave Simulator for the Design of Next-Generation High Performance
Systems
Steven L. Dvorak and John L. Prince, University of
Arizona, USA
11.4. Conceptual Simulator for Thermal Design of High Density Electronics
System
Y. Iwata, S. Yamamoto, S. Hayashi, and K. Fujimoto,
Osaka University
15:45 Closing Remarks