7th Workshop Technical Program
(Nov. 30-Dec. 2, 2004)

  Tuesday, November 30th, 2004  
9:50-10:30  Welcome & Invited Talks     Chair:  Masahiko Kohno

0.1. Opening Remarks
     Masahiko Kohno, Dow Chemical Japan Limited

0.2. Low-temperature Surface Activation Bonding in Microsystem Integration and Packaging
     Tadatomo Suga, The University of Tokyo, School of Engineering
10:30-12:00  Session 1:  Interconnect & Advanced Package-1     Co-Chairs:  Tomoshi Ohde and Len Schaper

1.1. Ultrafine-Pitch Solder Bumping and Flip-Chip Bonding
     Toshio Hamano and Katsumi Miyata, Fujitsu Ltd.

1.2. Low Temperature Bonding for Fine Pitch Flip Chip on Flexible Substrate Using Surface Activated Method
     Yao-Sheng Lin, Industrial Technology Research Institute

1.3. Electroplated AuSn Solder for Flip Chip Assembly and Hermetic Sealing
     Matthias Hutter, Maria von Suchodoletz, Hermann Oppermann, Gunter Engelmann, Oswin Ehrmann, and Herbert Reichl, Fraunhofer IZM
12:00-13:00  Lunch
13:00-15:30  Session 2:  Electrical Design     Co-Chairs:  Atsushi Nakamura and Rickey Lee

2.1. Electrical Performance Limitations of On-Package Decoupling Capacitors
     Leonard W. Schaper and Richard K. Ulrich, Univ. of Arkansas

2.2. Full Matrix Generation for Power Distribution Networks to Analyze Simultaneous Switching Noise
     Shin Suminaga and Narimasa Takahashi, IBM Japan, Ltd.

2.3. Study on the Efficiency of Transmission Line Structure for Fine Pitch Interconnection
     Takao Fujii*, Keisuke Saito, Yutaka Akiyama*, Tamotsu Usami, Kanji Otsuka*, and Tadatomo Suga, The Univ. of Tokyo, *Meisei Univ.

2.4. The Study of Electromagnetic Field of High Speed VLSI Package
     Chihiro Ueda and Kanji Otsuka*, AET Japan Inc., *Meisei Univ.

2.5. The Effectiveness of Guard Trace on Crosstalk Noise
     Chih-Wei Tsai, Hung-Hsiang Cheng, Chih-Yi Huang, Sung-Mao Wu, and C. P. Hung, Advanced Semiconductor Engineering, Inc.
15:30-15:45  Coffee break
15:45-18:15  Session 3:  Material & Substrate     Co-Chairs:  Hirofumi Nakajima and Phillip Garrou

3.1. Development of Capillary Underfill Material for Flip-Chip with Lead-Free Solder Bump and Low K Layer
     Masahiro Kitamura, Masahiro Wada, Katsushi Yamashita, Nobuaki Hayashi, and Yushi Sakamoto, Sumitomo Bakelite Co., Ltd.

3.2. Reworkable Secondary Underfill with High Reliability
     Yoshiyuki Takahashi, Yasunobu Matsumoto, Shoji Sasai, Sumitomo Bakelite Co., Ltd.

3.3. A New Sn/Ag Sintering Alloy Diffusion Bonding Technology for the PALAP Process
     Y. Yazaki, T. Yokochi, K. Suzuki*, and K. Kondo, Denso Corp., *NEC Electronics Corp.

3.4. Interconnection via Nanoporous Structure Utilizing Photoinduced Selective Plating Method for Ultra-thin-film Flexible Package Substrates
     Yasuyuki Hotta, Toshiro Hiraoka, Shigeru Matake, Misa Sawanobori, Ko Yamada, and Hiroshi Yamada, Toshiba Corp.

3.5. Flip Chip Substrate Trends for IC Packaging
     E. Jan Vardaman, TechSearch International, Inc.
18:30-20:30  Welcome Party     Co-Chairs:  Tomoshi Ohde and Masahiko Kohno
  Wednesday, December 1st, 2004  
9:00-10:30  Session 4:  Wafer-Level Packaging     Co-Chairs:  Tadaaki Mimura and E. Jan Vardaman

4.1. A Novel Q-factor Definition for Microwave Passive Elements
     Yutaka Aoki and Kazuhiko Honjo*, Casio Computer Co., Ltd., *Univ. of Electro-Communications

4.2. Development of Embedded Inductor in Wafer Level Chip Size Package
     Noritaka Anzai and Kiyonori Watanabe, Oki Electric Industry Co., Ltd.

4.3. The Proposal of WLP with Few Stress Damage to a Low-k Dielectric Material
     Tomio Matsuzaki, Casio Computer Co., Ltd.
10:30-10:45  Short Break
10:45-12:15  Session 5:  Interconnect & Advanced Package-2     Co-Chairs:  Nobuo Kamehara and Hiroshi Yamada

5.1. An Approach in Microbonding for Ultra Fine Pitch Application: Technology and Metallurgy
     Thomas Loher, Andreas Ostmann*, Rolf Aschenbrenner*, and Herbert Reichl, TU Berlin, *Fraunhofer IZM

5.2. Evaluation of Probing and Wire Bonding Effects on Active Circuits Under Bonding Pads
     Kuo-Ming Chen, Bing-Chang Wu, Leo KH Tan, Anthea Cheng, Nicholas Kao*, J-Y. Lai*, United Microelectronic Corp., *Siliconware Precision Industries Co., Ltd.

5.3. A New FCBGA Packaging Technology Based on the PALAP Process
     A. Hayashi, M. Nakagoshi, T. Murai, N. Sera, C. Ogihara, R. Oikawa, K. Suzuki, R. Kataoka*, and Y. Ozaki**, NEC Electronics Corp., *Denso Corp., **OK-print Corp.
12:15-13:15  Lunch
13:15-15:45  Session 6:  3D Packaging     Co-Chairs:  Masahiko Kohno and Hiroshi Manita

6.1. Process Development of Z-Axis Interconnects Using Fine Pitch Through Silicon Vias
     L. Schaper, S. Spiesshoefer, S. Burkett, G. Vangara, Z. Rahman, and S. Pollamreddy, Univ. of Arkansas

6.2. Electroless-Deposited Co-W-P Films for Chip Electrodes of Three Dimensional Packaging
     Koichi Hontake, Kazuo Kaieda*, and Hiroshi Kubota, Kumamoto Univ., *Yoshitama-Seito Corp.

6.3. Formation and Plugging of Through-Silicon-Vias for 3D Packaging
     S. W. Ricky Lee, Ronald Hon, Shawn X. D. Zhang, Sylvia, So, Hong Kong Univ. of Science & Technology

6.4. Improving Integrated Module Board Efficiency - Current Development in Imbera Electronics
     Risto Tuominen and Petteri Palm, Imbera Electronics Oy

6.5. Multi-Chip / Multi-Package Stacked Packaging Technology
     Jiro Kubota, Seiichiro Seki, and Kinya Ichikawa, Intel K.K.
15:45-16:00  Coffee Break
16:00-18:00  Session 7:  Thermal Design & Pb Free     Co-Chairs:  Michitaka Kimura and Rolf Aschenbrenner

7.1. Trend of Technology for Environment of Material for Electronic Equipment
     Nobuo Kamehara, Seiki Sakuyama, and Masayuki Ochiai, Fujitsu Ltd.

7.2. Lead-free Flip Chip Ball Grid Array Technology
     Takao Kaneko and Koichi Hirosawa, NEC Electronics Corp.

7.3. Next Generation Thermally Enhanced Plastic Ball Grid Array: An Application Driven Approach
     Ted Adlam, Jesse Galloway, Fred Hamilton, and Norito Umehara*, Amkor Technology, Inc.

7.4. A High-Speed Algorithm for Thermal Layout Design with Novel Thermal Management Method
     Shintaro Hayashi, Yoshiharu Iwata, Kozo Fujimoto, and Ryohei Satoh, Osaka Univ.
  Thursday, December 2nd, 2004  
9:00-10:30  Session 8:  RF & Opto MEMS-1     Co-Chairs:  Kanji Otsuka and Takeshi Takamori

8.1. Influence of Electromigration on the Reliability of Micro Switches
     Cheng-fu Chen, Naveen Kishore Karri, Boris Bracio, Univ. of Alaska Fairbanks

8.2. Packaging MEMS Accelerometers for Consumer Applications
     K. P. Harney, L. E. Felton, N. Hablutzel, and W. A. Webster, Analog Devices, Inc.

8.3. 2 GHz Linear Amplifier Module with Feedforward Linearizer on a Board
     Hiroyuki Kayano, Yuji Ohtsuka*, Masao Suzuki*, Masaya Ishiguro*, and Tatsunori Hashimoto, Toshiba Corp., *Toshiba Design & Manufacturing Service Corp.
10:30-10:45  Short Break
10:45-12:15  Session 9:  RF & Opto MEMS-2     Co-Chairs:  Noboru Iwasaki and Kaoru Kobayashi

9.1. Silicon Microlens for Optical Communications Component
     Masahiro Uekawa, Ryo Sekikawa, Daisuke Shimura, Kyoko Kotani, Yoshinori Maeno, Hironori Sasaki, and Takeshi Takamori, Oki Electric Industry Co., Ltd.

9.2. A System LSI Package with Optical I/O Interfaces for High-speed Interconnections
     Kazunori Miyoshi, Ichiro Hatakeyama, Tomoyuki Hino, Takanori Shimizu, Jun'ichi Sasaki, Keisuke Yamamoto, Mitsuru Kurihara, Takanori Watanabe, Jun Ushioda, and Kazuhiko Kurata, NEC Corp.

9.3. Analysis of Coupling between Vertical Feed Throughs in Multi-Layered Package
     Takeshi Yuasa, Tamotsu Nishino, Osami Ishida*, Hideyuki Oh-hashi, Mitsubishi Electric Corp., *Information and Communications Univ.
12:15-13:15  Lunch
13:15-15:45  Session 10:  Solder Joint & Reliability     Co-Chairs:  Toshio Sudo and George Harman

10.1. Degradation Mechanism of Preplated Leadframe under Atmosphere and Accelerated Aging Tests
     Young-Hee Kim, Jongwoo Park, Seung-Woog Wang, Seung-Woo Lee, and Hyun-Goo Jeon, Samsung Electronics

10.2. RF Substrate Via Relative Issue Discussion- Via and Ni/Au Surface Layer Crack
     Chien-Chen Lee, Kou-Ning Chiang, and C. H. Lin*, National Tsing Hua Univ., *Airoha Technology Corp.

10.3. Four-points Bending Method for Solder Joint Reliability Test under Mechanical Stress
     Kozo Harada, Shinji Baba, Qiang Wu, Yasumi Uegai*, Toshihiro Matsunaga*, and Michitaka Kimura, Renesas Technology Corp., *Mitsubishi Electric Corp.

10.4. Effect of 0.5 wt% Cu in Sn-3.5%Ag Solder on the Solid State Interfacial Reaction with the Au/Ni/Cu Bond Pad for Ball Grid Array (BGA) Application
     M. O. Alam and Y. C. Chan, City Univ. of Hong Kong

10.5. High Drop Test Reliability: Lead-free Solders
     Masazumi Amagai, Yoshitaka Toyoda*, Tsukasa Ohnishi*, and Satoru Akita*, Texas Instruments, Japan, *Senju Metal Industry Co., Ltd.
15:45  Closing Remarks