The 8th VLSI Packaging Workshop in Japan
Technical Program
(Dec. 4-5, 2006)

  Monday, December 4th, 2006  
9:30-10:30  Welcome & Invited Talks
                     Chair:  Tomoshi Ohde

0.1. Opening Remarks
     Tomoshi Ohde, Sony Computer Entertainment Inc.

0.2. Invited Talk, A Review of IBM's Semiconductor Packaging Technology
     Dr. Ashwani K. Malhotra, Semiconductor Packaging Senior Program Manager, Systems & Technology Group IBM Corp.
10:30-11:20  Session 1:  Functional Integration into Printed Wiring Boards
                       Co-Chairs:  Tomoshi Ohde and George Harman

1.1. Integrated Thin Film Capacitors in Organic Laminates
     Nobuo Kamehara, John D. Baniecki*, Takeshi Shioga*, Kazuaki Kurihara*, and Masataka Mizukoshi*, Fujitsu Quality Laboratory Ltd., *Fujitsu Laboratories Ltd.

1.2. Chip Embedding into Polymer Matrices of Printed Wiring Boards
     T. Loeher, A. Neumann, J.-P. Sommer, A. Ostmann, and H. Reichl, Technische Universitat Berlin and Fraunhofer IZM

11:20-12:35  Session 2:  Flipchip
                       Co-Chairs:  Michitaka Kimura and Rolf Aschenbrenner

2.1. Flip Chip with B-stageable Polymer Bump and Pre-applied Underfill for RFID Applications
     Bunya Watanabe, Dai Miyachika, Masanori Nakatoh, and Masataka Mizukoshi*, Emerson & Cuming Company, Ablestik Japan Co., Ltd., *Fujitsu Laboratories Ltd.

2.2. Fabrication on Extra-High Uniformity of Multiple Plating-Based Copper Pillars
     Pen-Shan Chao, Jung-Tang Huang, Hou-Jun Hsu, and Sheng-Hsiung Shih, National Taipei University of Technology

2.3. Failure Analysis of Solder Joint of FCBGA
     Keisuke Sato, Koichi Hirosawa, Katsunobu Suzuki, and Chika Kakegawa, NEC Electronics Corporation
12:35-13:30  Lunch
13:30-15:35  Session 3:  Signal and Power Integrity esign
                       Co-Chairs:  Toshio Sudo and Len Schaper

3.1. A Fast and Efficient Method for Impedance Estimation of Package-Board Power/Ground Network
     Jaemin Kim, Youchul Jeong, and Joungho Kim, KAIST

3.2. Power Optimization by Using Automatic Adjustment of the Driver Output Resistance for SIP Applications
     Amir Owzar, Ertan Baykal, and Markus Helfenstein, Philips Semiconductor

3.3. Backboard Transmission System Performed 6Gbps/450mm without Bypass Capacitor
     Takao Fujii, Yutaka Akiyama, Chihiro Ueda, Tsuneo Ito*, and Kanji Otsuka, Meisei University, *Excel Service Co.

3.4. Void Over Plated Through Hole (PTH) and Ball in Flip Chip Packages for Enhanced Signal Insertion, Return Loss and Delay Reduction
     Jiun Kai Beh, Ahmad Jalaluddin Bin Yusof, and Konika Ganguly, Intel Microelectronics Sdn. Bhd.

3.5. Improvement of LAN System Using 0.18��m CMOS Driver and Passive Equalizer
     Daisuke Iguchi, Yutaka Akiyama*, and Kanji Otsuka*, Fuji Xerox Co., Ltd., *Meisei University
15:35-15:50  Coffee Break
15:50-17:05  Session 4:  Thermal Integrity
                       Co-Chairs:  Atsushi Nakamura and Seok-Hwan HUH

4.1. Thermal Design of a High Power Multi-Chip Module
     Jesse Galloway, Sun Joong Kim, Frederick Hamilton, Tomoshi Ohde*, Kazuaki Yazawa*, Mitsuru Adachi*, Don Le**, Inderjit Singh**, Hideo Aoki***, and Eiichi Hosomi***, Amkor Technology, *Sony Semiconductor, **nVidia, ***Toshiba Corp.

4.2. Multi-Chip Package (MCP) Design Challenges for Future Technology
     Boon Howe Oh, Eng Kwong Lee, Howe Yin Loo, and Poh Tat Oh, Intel Microelectronics Sdn. Bhd.

4.3. Spatial and Transient Thermal Spreading Model for a VLSI Package
     Kazuaki Yazawa, Tetsuji Tamura, Iwao Takiguchi, and Tomoshi Ohde, Sony Computer Entertainment Inc.

17:05-18:20  Session 5:  Micro Optical Packaging
                       Co-Chairs:  Takeshi Takamori and Shigenori Aoki

5.1. Performance and Demonstration of Optical Lines Fabricated in Electrical Substrate
     Maraki Maetani, Takahiro Matsubara, Keiko Oda, Keiichiro Watanabe, Kaori Tanaka, Yuriko Nishimura and Shigeo Tanahashi, Kyocera Corporation

5.2. ��BOSA Chip with Si Microlens for Low Cost Bi-directional Optical Modules
     Ryo Sekikawa, Daisuke Shimura, Masahiro Uekawa, Kyoko Kotani, Yoshinori Maeno, Katsumi Aoyama, Hironori Sasaki, Koichiro Masuko*, and Teijiro Ori*, Oki Electric Industry Co., Ltd., *SIGMA-LINKS INC.

5.3. Low Cost Surface Mount Optical Multi Chip Module
     Tomoki Umezawa, Kenji Yamazaki, Yasuhiro Sato, Daisuke Iguchi, and Ryousuke Okimura*, Fuji Xerox Co., Ltd., *Suzuka Fuji Xerox Co., Ltd.
18:20-20:20  Welcome Party
                       Co-Chairs:  Michitaka Kimura and Tomoshi Ohde

  Tuesday, December 5th, 2006  
9:00-10:15  Session 6:  3D Pb free beyond RoHS
                       Co-Chairs:  Tadaaki Mimura and Nobuo Kamehara

6.1. Alloying Behavior of Ag/Sn and Cu/Sn Electroplated Stacks for Lead-Free Bumping
     Hirokazu Ezawa, Kazuhito Higuchi, Masaharu Seto, Masayuki Uchida, and Takashi Togasaki, Toshiba Corporation

6.2. An Examination of BGA's Acceptable Warpage at High Temperature
     Hiroshi Kawakubo, Renesas Technology Corp.

6.3. Advanced Warpage Control for DRAM Package
     Masanori Shibamoto, Masahiro Yamaguchi, Hisashi Tanie*, and Hideyuki Chaki**, Elpida Memory Inc, *Hitachi Ltd. **Hitachi Chemical Co., Ltd.
10:15-10:30  Short Break
10:30-12:10  Session 7:  Advanced Materials for Thermal and Mechanical Issues
                       Co-Chairs:  Masahiko Kohno, Kaoru Kobayashi and Rickey Lee

7.1. Fabrication of the AlN+Al Composite for a Heat-Sink Substrate for Semiconductor Devices
     Y. Oya-Seimiya, T. Shinoda, and K. Otsuka, Meisei University

7.2. Development of Bending Strength Test Simulation of Printed Circuit Board, and Analysis of the Process When Defectiveness Occurs
     Tomoyuki Kosugi and Tomio Matsuzaki, Casio Computer Co., Ltd.

7.3. Fusion Solution for Advanced FC Package
     Hitoshi Kawaguchi, Sumitomo Bakelite Co., Ltd.

7.4. Reliability Evaluation of the New Polyimide Multilayer Substrate
     Hideyuki Fujinami, Shoji Ito, Hiroshi Kutami, Osamu Nakao, and Nobuyuki Sadakata, Fujikura Ltd.
12:10-13:10  Lunch
13:10-13:30  Award Ceremony
13:30-15:35  Session 8:  Advanced 3-D Packaging Technology toward Next Generation
                       Co-Chairs:  Hiroshi Manita and Hiroshi Yamada

8.1. Si Scaling Impacts on Junction Temperature
     Jotaro Akiyama and Masazumi Amagai, Texas Instruments Japan Ltd.

8.2. Resin Spacer Material Characterization for Stacked Die Package
     Kenji Abe and Masazumi Amagai, Texas Instruments Japan Ltd.

8.3. Development of Through Silicon Vias Technology for Device Wafer
     Masahiro Sunohara and Mitsutoshi Higashi, Shinko Electric Industries Co., Ltd.

8.4. Development of Stacked Memory Chip Process Technology
     T. Mitsuhashi, S. Uchiyama*, N. Takahashi**, Y. Egawa, Y. Saeki, O. Kato, H. Kikuchi, A. Yanagisawa, K. Shibata*, J. Yamada*, M. Ishino*, H. Ikeda*, Y. Kurita**, M. Komuro**, S. Matsui**, and M. Kawano**, Oki Electric Industry, *Elpida Memory, **NEC Electronics

8.5. Systems in Miniature: Meeting the Challenges of 3-D VLSI
     L. Schaper, S. Burkett, M. Gordon, L. Cai, J. Patel, T. Lam, I. U. Abhulimen, and T. Rowbotham, University of Arkansas
15:35-15:50  Coffee Break
15:50-17:30  Session 9:  High Density Packaging Technology and Reliability
                       Co-Chairs:  Atsushi Okuno and E. Jan Vardaman

9.1. Package Stackable CSP Development for Package on Package (PoP)
     Akito Yoshida, Moody Dreiza, and Jun Taniguchi, Amkor Technology

9.2. Ultrafine-Pitch Bump Interconnection on Chip-On-Chip Package
     Toshihiro Iwasaki, Masaki Watanabe, Shinji Baba, Yasumichi Hatanaka*, Shiori Idaka*, Yoshinori Yokoyama*, and Michitaka Kimura, Renesas Technology Corporation, *Mitsubishi Electric Corporation

9.3. Effect of Mild Aging on Solder Joint Interface Failure
     Robert Darveaux, Corey Reichman, Parul Agrawal*, and Se Woong Cha**, Amkor Technology, Inc., *Arizona State University, **Amkor Technology Korea

9.4. FEA Modeling and DOE Analysis for Design Optimization of High-end SiP
     Chika Kakegawa, Sang Ha Kim*, Hiroshi Tabuchi, and Masaki Yajima, NEC Electronics Corporation, *NEC Electronics America, Inc.
17:30  Closing Remarks