9th Workshop Technical Program
(Dec. 1-2, 2008)

Monday　Dec. 1

09:30 - 10:15               Welcome and Invited Talk
　　　　Chair:        Michitaka Kimura,    Renesas Technology Corp.

0.1 Opening Remarks     Michitaka Kimura        Renesas Technology Corp.
0.2

Invited Talk, 3D-SiP: the latest Miniaturization Technology ,
Leonard W. Schaper University of Arkansas


10:15 - 11:05           Session 1: Advanced Packaging                 
　　　　Co-Chairs: Michitaka Kimura & Len Schaper

1.1

Stretchable electronic systems for wearable and textile applications,
Thomas Löher, Rene Vieroth, Manuel Seckel, Andreas Ostmann*, and Herbert Reichl*,
Technische Universität Berlin, Fraunhofer-IZM*
1.2 SLC-Based Optical Interconnect for Computing Systems,
Shigeru Nakagawa, Yoichi Taira, Hidetoshi Numata, Kaoru Kobayashi*, Kenji Terada* and Yutaka Tsukada*,
IBM Tokyo Research Laboratory, Kyocera

11:05 - 12:05           Tutorial Session                 
　　Co-Chairs: Takeshi Takamori and Tadaaki Mimura  


TS.1

Description of meta-material phonoma (deployment of the bold logic by the Otsika personal opinion),
Kenji Otsuka, Meisei Unversity

12:05-13:00 Lunch

13:00-15:05             Session 2: Thermal Design               
　　　Chair: Nobuo Kamehara

2.1 Accurate Junction Temperature prediction method for plastic LSI packages,
Naoto Taoka, Atsushi Nakamura and Masao Urase*,
Renesas Technology Corp., Wave Technology Inc*.
2.2 Solder Joint Lifetime Evaluation of WLP and Cause Investigation,
Tomio Matsuzaki,
Casio Computer Co., Ltd
2.3 A Study of material properties for Package Flatness in 3D Package,
Yutaka Suzuki and Masazumi Amagai,
Texas Instruments Japan Limited Tsukuba Technology Center
2.4 Enabling Dynamic Voltage & Frequency Scaling In Next-Generation Microprocessors: Thermal & Reliability Considerations,
Sai Ankireddi and David Copeland,
Sun Microsystems
2.5 Material property calculation of interposer card for modeling of Package-on-Package,
M.Kuzuno, H.Noma and T.Nishio*,
High Density Packaging Technology, Global Engineering Solutions AP Delivery, Global Engineering Solutions,* IBM Japan, Ltd.

15:05-15:20 Coffee Break

15:20 - 16:10           Session 3: Mechanical Design                                      
　　Co-Chairs: Takeshi Takamori and Tadaaki Mimura  


3.1 Numerical Analysis and Experimental Validation for the Prediction of Flip Chip Solder Joint Standoff Height in MEMS Microphone Application,
Jeffery C. C. LO and S. W. Ricky LEE,
Electronic Packaging Laboratory Center for Advanced Microsystems Packaging Hong Kong University of Science and Technology
3.3

Prediction of Board Level Reliability of Drop Test for System-in-Package,
Eiichi Yamada and Masazumi Amagai, Texas Instruments Japan Limited Tsukuba Technology Center


16:10-16:30 Coffee Break

16:30 - 18:35           Session 4: Signal and Power Integrity  
　　　　Chair: Atsushi Nakamura


4.1 Enhanced Power Supply Structure with New Mesh Wiring and Electroless Plated Shunt Line and Assembly-Stress-Relaxation Structure,
Taichi Nishio, Kazuhiro Ishikawa, Fumito Itoh, Yutaka Itoh, Chikako Karatani, Koji Koike, Yukitoshi Ota, Masao Takahashi and Hiroshige Hirano,
Panasonic Corporation.
4.2 Development of Low Characteristic Impedance Transmission Line for Power Supply,
Kaoru Hashimoto, Yutaka Akiyama, Toshiyuki Kawaguch*i, Kazutoki Tahara*, and Kanji Otsuka,
Meisei University, Shin-Etsu Polymer Co., Ltd *
4.3 Experimental Verification and Analysis for Noise Isolation of Analog and Digital Chip-Package-PCB Hierarchical Power Distribution Network,
Hyunjeong Park, Jongjoo Shim, Yujeong Shim, Jeongsik Yoo and Joungho Kim,
Terahertz Interconnection and Package Lab., School of Electrical Engineering & Computer Science, Division of Electrical Engineering, KAIST
4.4 A Chip Stacking Technology Utilizing Transmission Line Coupling,
Daisuke Iguchi, Yutaka Akiyama*, Tsuneo Ito** and Kanji Otsuka*,
Fuji Xerox Co., Ltd.*Meisei University*, Excel Service Co.**
4.5 A Study on High-Speed Transmission Characteristics of Interconnections from PCB to Chip,
k. Yamagishi, T. Ishibashi*, H. Ohashi and S. Saito,
Mitsubishi Electric

18:40 - 20:40 Welcome Party

Tuesday　Dec. 2

09:00 - 10:40              Session 5: Flip Chip and Interconnection
　　　　Chair: Hirofumi Nakajima

5.1 Chip Package Interaction Analysis for Cu/Ultra Low-k Large Die Flip Chip Ball Grid Array,
Chihiro J. UCHIBORI, Michael Lee, Xeufeng Zhang* and Paul S. Ho*,
Fujitsu Laboratories of America, Inc., Microelectronics Research Center, University of Texas at Austin*
5.2 The Chip-on-Board Bonding Using Non-Conductive Film and Metallic Bumps by the Surface Activated Bonding Method,
Ying-Hui Wang and Tadatomo Suga,
School of Engineering, the University of Tokyo
5.3 MPS-C2 and Post Encapsulation Grinding Technology for Ultra Fine Pitch and Thin Die Flip Chip Applications
Yasumitsu Orii, Kazushige Toriyama, Yukifumi Oyama and Toshihiko Nishio,
Microlectronics Division, IBM Japan Ltd.
5.4 New Developments in Flip Chip,
E. Jan Vardaman,
TechSearch International, Inc.

10:40-10:55 Coffee Break

10:55 - 12:35           Session 6: Advanced Material                                   
　　　　Chair: Kanji Otsuka

6.1 Electrochemical Migration of Electronic Components at Sea Environments - Characterization and Solutions,
Mohamed A. Hussain and Fuad M. Khoshnaw*,
University of Sulaimani , Loughborough University*
6.2 Unique high reliability urethane resin for car electronic module packaging,
Y.Takei, K.Ueda, N.Hisanaga, H.Nakata, K.Isi, T.Nagi and Atsushi Okuno,
Sanyu Rec Co.,
6.3 Effect of Rare Earth Elements Doping on the Electrical Properties of (Ba,Sr)TiO3 Thin Film Capacitors,
N. Kamehara and K. Kurihara,
Fujitsu Quality Laboratory LTD., Fujitsu Laboratories LTD.,
6.4 Highly reliable silicone TIM for CPU package - Silicone curable grease- ,
Kei Miyoshi, Kunihiro Yamada and Kenichi Isobe,
Shin-Etsu Chemical Co., Ltd.

12:35-13:35 Lunch

13:35-14:05 Award Ceremony                                          

14:05 - 15:45           Session 7: Embedded Device and IPD
　　　　Co-Chairs: Shigenori Aoki and Hiroshi Manita

7.1

Comparative Stress Analysis of A Innovative Package with Embedded Die Substrate,
Albert Ou, Y.H. Wang, C.C. Fu, C.J. Hsu and C.L. Kao,
Advanced Semiconductor Engineering, Inc
7.2 Si Interposers Integrated with SrTiO3 Thin Film Decoupling Capacitors and Through-Si-Vias,
Koichi Takemura, Akira Ohuchi and kinobu Shibuya,
Device Platforms Research Laboratories, NEC Corporation
7.3 Reliability of polyimide-based Thin and Flexible Capacitors with SrTiO3,
Yasuhiro Ishii, Toru Mori, Akinobu Shibuya and Koichi Takemura,
Device Platforms Research Laboratories, NEC Corporation
7.4 Analysis of High Performance RF Integrated Passive Circuits Using the Glass Substrate,
Chen-Chao Wang, Hsueh-An Yang, Ying-Chieh Shyu, Meng-Hsun Li , Chi-Tsung Chiu and Chih-Pin Hung,
Advanced Semiconductor Engineering Inc,

15:45-16:00 Coffee Break

16:00 - 17:15           Session 8: 3-D Packaging                                               
　　　　Co-Chairs: Hiroshi Yamada and E. Jan Vardaman

8.1 Room Temperature Wafer Bonding Using Surface Activated Bonding Method,
Shingo Taniyama, Ying-Hui Wang, Masahisa Fujino and Tadatomo Suga,
School of Engineering, the University of Tokyo
8.2 Integrated System Development for 3-D VLSI,
Leonard Schaper, Yang Liu, Susan L. Burkett*, Alphonse Kamto*, Gayathri Jampana**, Susan Jacob and
Isibhakhomen Umolu Abhulimen*** ,
University of Arkansas,Department of Electrical Engineering, University of Alabama*, Brewer Science**, Intel Corp.***
8.3 High Density Assembly Technology using Stacking Method,
Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Eiri Hashimoto, Shinjiro Toyoda and Nobuaki Miyakawa,
Honda Research Institute Japan Co., Ltd.

17:15        Closing Remarks

 Last updated:  2009/ 3/27